1. Field of the Invention
The invention relates to a semiconductor integrated circuit for supplying optimized power supply voltages to an internal circuit group.
2. Description of the Related Art
Generally, a semiconductor integrated circuit includes a plurality of logic circuits, one of which is a Central Processing Unit (CPU) for which a high speed arithmetic process with low power consumption is demanded. In such a semiconductor integrated circuit, through a semiconductor manufacturing process, namely a wafer process, transistors or its wirings are not manufactured uniformly among the chips. This means that the production tolerance may be occurred during the wafer process.
Because of the production tolerance, when a drain/source current value is set at smaller than that being expected, the arithmetic process speed of the CPU becomes slow. To prevent the processing speed of the CPU from slowing, a high voltage is applied for increasing the drain/source current value. On the other hand, when a drain/source current value is set at higher than that being expected, the power consumption by the CPU becomes larger. To prevent the power consumption of the CPU from becoming larger, a low voltage is applied.
According to a non patent literature document (Reference 1), which is listed below, a semiconductor integrated circuit in a form of a chip includes logic circuits, a process monitoring circuit, a trimming logic circuit for generating a trimming logic signal, such as a voltage regulating circuit for optimizing the voltage value. The semiconductor integrated circuit disclosed in the Reference 1 optimizes the voltage value for each chip, which is manufactured in the different lot, by activating the process monitoring circuit in response to the production tolerance. Since the semiconductor integrated circuit generates a few-bit trimming signal by which a power supply voltage generating circuit generates such an optimized voltage, the power supply voltage generating circuit generates the optimized voltage internally corresponding to the trimming signal, and supplies such an optimized voltage to the internal logic circuits.
Further, according to a Japanese patent publication (Reference 1), which is also listed below, a delay-time measuring circuit in a power supply voltage supplying device sends a first pulse to a delay circuit provided in a semiconductor device and measures the estimated value of the delay time of the semiconductor device from a second pulse, which is the response signal of the first pulse. Then, in response to the measuring result, the power supply control circuit determined the optimized power supply voltage, which is applied to the semiconductor device.
Reference 1: Nikkei Electronics 2006.7.17, vol. 930, page at 59, published by Nikkei BP
Reference 2: Japanese Laid open patent publication No. H08-136621A
Moreover, because of influence of the process tolerance, the transistors formed in the same wafer are not manufactured uniformly as well as the transistors formed in the different lot. In other words, there are variations of characteristics of each transistor formed in the single wafer. Recent years, because of the miniaturization of the chip, the process tolerance bears influence on the internal circuits. The process tolerance is caused by a dislocation of a resist mask in a photolithography process or by a failure for controlling the film formation process or the planarization process.
However, the conventional semiconductor integrated circuit disclosed in the Reference 2 can have only one place where the delay-time measuring circuit is disposed. Thus, even when the power-supply voltages values having different values should be applied to circuits formed in the single chip, respectively, because of the result of the process tolerance, the gap among the values of the power-supply voltages cannot be corrected.
Moreover, the process monitoring circuit is relatively large scale circuit because it has a lot of functions, such as detecting monitoring data, processing serial signals, and generating trimming logics. Thus, when a plurality of the delay-time measuring circuits are disposed, the same numbers of the large scaled process monitoring circuits are required. An increase of the monitor circuits causes to increase of the number of wiring for the trimming logics to be transmitted, and to increase of the area of the chip.
Moreover, when the power supply voltage is varied in response to each trimming logic in the power supply voltage generating circuit, the correction of the power supply voltage is made by correction signals passing through terminals specialized for the correction signals for every voltage to be corrected. Thus, such terminals should be formed in the chip so that the area of the chip is further increased.